The present invention relates to semiconductor devices and a method for making them.
How an MOS transistor""s source and drain junctions are oriented with respect to the gate electrode may significantly affect the performance of sub 0.1 micron MOS devices. The source and drain regions for MOS transistors are conventionally formed by implanting dopants into a silicon substrate, then applying heat to cause those dopants to diffuse vertically and laterally within the substrate. This process does not generate junctions with sharp edges, as implant straggle and the nature of the diffusion process make it difficult to precisely control their location. Another issue relates to solid solubility considerations that limit the doping concentrations that may be achieved using such an ion implant process.
Accordingly, there is a need for a method for making an MOS device that includes a source and drain with sharp junctions and a controlled doping profile. There is also a need for a method for making such a device in which doping concentrations may exceed the solid solubility limits for a given dopant and substrate. The method of the present invention provides such a process.
The present invention covers a method for making a semiconductor device. In that method, source and drain regions are epitaxially grown on a first part of a substrate. A gate oxide is then formed on a second part of the substrate. After the gate oxide is formed, an etched polysilicon layer is formed on the gate oxide.